1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device including a level shifter for converting a signal as inputted to a signal having a greater voltage amplitude.
2. Description of the Background Art
As a result of the recent development in technologies for finer semiconductor processing, the number of transistors that can be integrated on a single chip in a semiconductor integrated circuit device has drastically increased, which in turn causes increase of power consumption. In order to reduce power consumption, it is requisite to reduce a power supply voltage. To take a MOS (metal oxide semiconductor) transistor as an example, which is one of the most prevailing field effect transistors in the recent days, the minimum design rule thereof has decreased from 0.25 μm to 0.18 μm, and further decreased from 0.18 μm to 0.15 μm up to these days, which has been followed by decrease of a power supply voltage from 2.5V to 1.5V via 1.8V. Since such power supply voltage as decreased is utilized for a core portion in an integrated circuit, it will be hereinafter referred to as a power supply voltage VDD of a core circuit in the following description.
On the other hand, an interface portion provided for exchanging signals with another chip is supplied with another power supply voltage VDDH having a constant value which is kept higher than the power supply voltage VDD of the core circuit, notwithstanding the development in the techniques for semiconductor processing. Recently, a 3.3V-voltage is used as the power supply voltage VDDH in most cases. The reasons for using the power supply voltage VDDH for the interface portion are that: all transistors on each chip mounted on a board are not manufactured using the most advanced technologies for semiconductor processing; and a change in standards for the interface portion probably causes considerable confusion. However, it is impossible to have a transistor(s) in the core portion which is manufactured using the most advanced technologies operate with a 3.3V-power supply voltage. In this regard, as for a transistor(s) in the interface portion, the film thickness of a gate oxide film thereof is increased to increase a breakdown voltage of a gate thereof, as compared with that in the core portion, while permitting performance of the device to be degraded due to the increase in film thickness of the gate oxide film.
To use more than two kinds of power supply voltages in one integrated circuit device for the reasons noted above would require a level shifter for changing an amplitude of a signal between circuit blocks different from each other in power supply voltage used therein.
FIG. 11 shows a conventional semiconductor integrated circuit device including a level shifter. A signal Din is a digital signal generated within a core circuit 2, high and low levels of which signal are equal to a level of the power supply voltage VDD and a level of a ground voltage GND, respectively. The core circuit 2 generates two pairs of logically complementary signals based on the signal Din through logic gates IN0, IN1, IN2, G0 and G1. Each of the signals to be generated has a voltage amplitude identical to that of the signal Din. A level shifter 16 receives one of the pairs of complementary signals at gate electrodes of NMOS transistors N0 and N1, while a level shifter 18 receives the other pair of complementary signals at gate electrodes of NMOS transistors N2 and N3.
One logic is inputted to each gate of the NMOS transistors N0 and N2 and another logic reverse to the one logic is inputted to each of the NMOS transistors N1 and N3. Accordingly, the level shifters 16 and 18 output signals which have the same logic and swing between levels of the power supply voltage VDDH and the ground voltage GND, from nodes D1 and D2, respectively. In accordance with the signals outputted from the level shifters 16 and 18, a PMOS transistor PD and an NMOS transistor ND of a driver portion 10 are turned ON in a complementary manner.
When an enable signal EN represents a high logic level, a signal Dout having the same logic as that of the signal Din and having a greater amplitude than that of the signal Din is present on a node 23 with the foregoing operations having been followed. When the enable signal EN represents a low logic level, the PMOS transistor PD and the NMOS transistor ND of the driver portion 10 are simultaneously turned OFF, so that the node 23 is put in a high-impedance state.
As described above, when more than two kinds of power supply voltages are used in a semiconductor integrated circuit device, the PMOS transistor PD and the NMOS transistor ND may possibly be simultaneously turned ON at the time of power supply, depending on which portion of the device is supplied with power earlier. For the supply of power, a power supply voltage is applied to an external power source terminal of the semiconductor integrated circuit device, so that the potential of a power node within the device is raised from the level of the ground voltage to the level of the power supply voltage.
In an situation where the power supply voltage VDDH is applied to an interface portion 4 after the power supply voltage VDD is applied to the core circuit 2, no problem would arise. In that situation, the logic levels of the two pairs of signals to be sent from the core circuit 2 to the interface portion 4 are determined prior to application of the power supply voltage to the interface portion 4. Hence, there is no possibility that the PMOS and NMOS transistors PD and ND are simultaneously turned ON. Accordingly, no current flowing through the transistors PD and ND is caused. However, in an situation contrary to the foregoing case, where the power supply voltage VDD is applied to the core circuit 2 after the power supply voltage VDDH is applied to the interface portion 4, a problem will arise as below.
At the time when the power supply voltage VDDH is applied to the interface portion 4, each potential of the gate electrodes of the NMOS transistors N0 and N1 of the level shifter 16 is kept at a low logic level (i.e., the level of GND). Accordingly, a potential of the node D1 as an output terminal is indefinite and may possibly be set at a low logic level (i.e., the level of GND), for example. Likewise, since each potential of the gate electrodes of the NMOS transistors N2 and N3 of the level shifter 18 is kept at a low logic level at the time of power supply, a potential of the node D2 as an output terminal is indefinite and may possibly be set at a high logic level (i.e., the level of VDDH), for example. With the potentials of the nodes D1 and D2 being set as such, the PMOS transistor PD and the NMOS transistor ND are simultaneously turned and kept ON until levels of signals to be respectively inputted from the level shifters 16 and 18 are determined. Each of the transistors PD and ND functioning as an output driver is configured so as to have a grater driving force than that of any other transistor having a different function. For this reason, when the PMOS transistor PD and the NMOS transistor ND are simultaneously turned ON, it results in generation of a large amount of current flow. The large amount of current flow is likely to cause wire-disconnection or the like, leading to destruction of the semiconductor device.